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Results 1 to 25 of 936

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Balancing electrical and optical interconnection resources at low levelsDRABIK, T. J.SPIE proceedings series. 1998, pp 556-559, isbn 0-8194-2949-XConference Paper

A fast, single-layer, area router for semi-custom analogue circuitsBUSET, O; DECLERCQ, M; FOUAD RAHALI et al.International journal of circuit theory and applications. 1992, Vol 20, Num 3, pp 283-298, issn 0098-9886Article

Standards for keyboard layout―the origins and scope of ISO/IEC 9995PATERSON, B.ICL technical journal. 1992, Vol 8, Num 2, pp 316-331, issn 0142-1557Article

On internal-external layoutsTOLLIS, I. G.IEEE transactions on circuits and systems. 1989, Vol 36, Num 1, pp 154-156, issn 0098-4094, 3 p.Article

Sélection des fondations de ponts pour s'accorder aux conditions géologiques et topographiquesOSHIMA, K.Tsuchi to kiso. 1986, Vol 34, Num 9, pp 9-12, issn 0041-3798Article

Removing edge-node intersections in drawings of graphsWEI LAI; EADES, Peter.Information processing letters. 2002, Vol 81, Num 2, pp 105-110, issn 0020-0190Article

TILT, a technology independent layout toolRIEM-VIS, R; MALIKI, G; PELLANDINI, F et al.AGEN-Mitteilungen. 1992, Num 55, pp 29-38, issn 1016-1554Conference Paper

Graph layout for displaying data structuresWADDLE, Vance.Lecture notes in computer science. 2001, pp 241-252, issn 0302-9743, isbn 3-540-41554-8Conference Paper

Cell-based layout techniques supporting gate-level voltage scaling for low powerYEH, Chingwei; KANG, Yin-Shuin.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 5, pp 629-633, issn 1063-8210Conference Paper

REX «Guise II» Métrologie de chantier. 118 logements PLA à Dijon (21): Rapport de suivi/évaluation = REX «Guise II». Site metrology. 118 local authority flats in Dijon: Progress/assessment reportSALAGNAC, J.L.1997, 68 p.Report

On the effect of floorplanning on the yield of large area integrated circuitsKOREN, Z; KOREN, I.IEEE transactions on very large scale integration (VLSI) systems. 1997, Vol 5, Num 1, pp 3-14, issn 1063-8210Conference Paper

Incremental layout placement modification algorithmsCHOY, C.-S; CHEUNG, T.-S; WONG, K.-K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 4, pp 437-445, issn 0278-0070Article

REX métrologie de chantier: Rapport final = Construction site metrology: final report1996, 31 p.Report

A high-sensitivity MOS photo-transistor for area image sensorMATSUNAGA, Y; YAMASHITA, H; MANABE, S et al.I.E.E.E. transactions on electron devices. 1991, Vol 38, Num 5, pp 1044-1047, issn 0018-9383Article

A microwave circuit for a 1 V Josephson voltage standard operated at 35 GHzMÜLLER, F; KÖHLER, H.-J; WEBER, P et al.Physica status solidi. A. Applied research. 1990, Vol 121, Num 1, pp K73-K75, issn 0031-8965Article

Bit-serial parallel processing unit for the histogramming operationABDELGUERFI, M; KHALAF, S; SOOD, A. K et al.IEEE transactions on circuits and systems. 1990, Vol 37, Num 7, pp 948-954, issn 0098-4094Article

Status of the short dipole model program for the LHCARTOOS, K; BOTTURA, L; WYSS, C et al.IEEE transactions on applied superconductivity. 2000, Vol 10, Num 1, pp 49-52, issn 1051-8223Conference Paper

Generating layouts for self-implementing modulesHWANG, J; PATTERSON, C; MOHAN, S et al.Lecture notes in computer science. 1998, pp 525-529, issn 0302-9743, isbn 3-540-64948-4Conference Paper

Low power, process independent, full transistor controlled slew rate, PCI compliant I/O padsWAJSBÜRT, F; DIOURY, K; PETROT, F et al.International conference on microelectronic. 1997, pp 811-814, isbn 0-7803-3664-X, 2VolConference Paper

Altes Layout im neuen Prozess = The use of layout-to-layout compaction for design reuseKLAVER, S; FILARSKY, S.F & M. Feinwerktechnik, Mikrotechnik, Messtechnik. 1996, Vol 104, Num 11-12, pp 796-797, issn 0944-1018Article

A framework for industrial layout generatorsBOWER, W; SEAQUIST, C; WOLF, W et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 5, pp 596-603, issn 0278-0070Article

On river routing with minimum number of jogsTUAN, T. C; TEO, K. H.IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 2, pp 270-273, issn 0278-0070, 4 p.Article

Geometric approach to VLSI layout compactionXIAO-MING XIONG; KUH, E. S.International journal of circuit theory and applications. 1990, Vol 18, Num 4, pp 411-430, issn 0098-9886Article

An algorithm for polygon conversion to boxes for VLSI layoutsAL-KHALILI, A. J; AL-KHALILI, D; AMMAR et al.Integration (Amsterdam). 1988, Vol 6, Num 3, pp 291-308, issn 0167-9260Article

GPE: A new representation for VLSI floorplan problemLIN, Chang-Tzu; CHEN, De-Sheng; WANG, Yi-Wen et al.Proceedings, IEEE International Conference on Computer Design. 2002, pp 42-44, issn 1063-6404, isbn 0-7695-1700-5, 3 p.Conference Paper

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